Set the FIFO control registers.
This is a specific operation of the generic operation lv1_gpu_context_attribute(...);
This call is unused by the kernel. It has been discovered by probing.
| Inputs | |
|---|---|
| Register | Description |
| R3 | ps3fb.context_handle as allocated by lv1_gpu_context_allocate theoretically. |
| R4 | operation_code - L1GPU_CONTEXT_ATTRIBUTE_FIFO_SETUP (0×001) |
| R5 | PUT pointer |
| R6 | GET pointer |
| R7 | REF pointer |
| R8 | unused |
| Outputs | |
| Register | Description |
| R3 | Status - 0 = OK, Other values are unknown, but indicate failure. |
The PUT, GET and REF pointers can also be accessed from the lpar_dma_control region obtained from the lv1_gpu_context_allocate call. Their relative offsets are the following:
| Offset | Register | Description |
|---|---|---|
| 0×40 | PUT | Pointer to last command written to the GPU. Owned by CPU. |
| 0×44 | GET | Pointer to last command read by the GPU. Owned by GPU. |
| 0×48 | REF | Unknown. |
| 0×54 | TOP | Unknown. Owned by GPU. |
Setting the PUT pointer to a different value than the GET pointer will trigger the GPU. It will process FIFO commands, increasing the GET and TOP pointers as they are read until they both reach the value of the PUT register. Note that when GET equals PUT, it does not mean all commands are complete, only they have been read. The TOP pointer is lagging a bit behind the PUT pointer; its usage is unknown.
Setting the PUT pointer to 4 crashes the GPU (as expected), but also seems to trigger some sort of crash dump in the lpar_driver_info region of lv1_gpu_context_allocate. This needs further investigation.