This structure is returned by the lv1_gpu_context_allocate function as a substructure of gpu_driver_info
struct gpu_irq {
u32 irq_outlet;
u32 status;
u32 mask;
u32 video_cause;
u32 graph_cause;
u32 user_cause;
u32 res1;
u64 res2;
u32 reserved[4];
};
| Member | Description |
|---|---|
| irq_outlet | This is used for parameter 4 to lv1_connect_irq_plug_ext to associate the irq with the GPU ??? Unsure ??? |
| status | Unknown, Unused by the Kernel. |
| mask | Mask off IRQ sources from the GPU. This is a bitset. A bit = 0 means IRQ masked, 1 = IRQ enabled. Bit GPU_INTR_STATUS_VSYNC_0 = 0. IRQ for vsync on head A. Unused by Kernel Bit GPU_INTR_STATUS_VSYNC_1 = 1. IRQ for vsync on head B. Used by Kernel Bit GPU_INTR_STATUS_FLIP_0 = 2. IRQ for flip on head A. Unused by Kernel Bit GPU_INTR_STATUS_FLIP_1 = 3. IRQ for flip on head B. Used by Kernel Bit GPU_INTR_STATUS_QUEUE_0 = 4. IRQ for queue on head A. Unused by Kernel Bit GPU_INTR_STATUS_QUEUE_1 = 5. IRQ for queue on head B. Unused by Kernel |
| video_cause | Unknown, Unused by the Kernel. |
| graph_cause | Unknown, Unused by the Kernel. |
| user_cause | Unknown, Unused by the Kernel. |
| res1 | Unknown, Unused by the Kernel. |
| res2 | Unknown, Unused by the Kernel. |
| reserved[4] | Unknown, Unused by the Kernel. |
This structure seems to hold information about the IRQ’s from the GPU and to also allow them to be “hooked” and “masked”, as well as providing information about what IRQ has occured.
An Example of enabling the VSYNC_1 and FLIP_1 IRQ using the constants specified in mask is:
irq.mask = (1 << GPU_INTR_STATUS_VSYNC_1) | \\
(1 << GPU_INTR_STATUS_FLIP_1);